1. Field of the Invention
The present invention relates to computer systems for simulating (see definitions sections) the performance of electronic circuits and more particularly to computer software for simulating on-chip interconnects and/or other conductors that behave as transmission lines.
2. Description of the Related Art
Certain electrical conductors behave as transmission lines. When conducting electrical signals, these conductors exhibit far end response characteristics (see Definitions section), such as frequency dependent effects, step response, ramp response, delay, 50% delay, rise time, 10% to 90% rise time, overshoot and normalized overshoot. Designers of systems using transmission lines often must take various far end response characteristics into account in the circuit design. For example, on-chip interconnects exhibit significant transmission line behavior, especially with the scaling of CMOS technology and its associated high performance integrated circuits (ICs), which use relatively high frequencies and relatively long wire lengths.
For CMOS IC on-chip interconnect design, on-chip interconnect design more generally, and even other types of transmission line design, the circuits are simulated on computer systems, as they are designed. The computer system (generally in its software component) allows the designer to simulate transmission lines and to determine or estimate the far end characteristics. In this way, the timing characteristics sent over the transmission lines can be determined, preferably with sufficient accuracy and precision so that the design (for example, CMOS IC chip design) will work for its intended purpose at its operating frequency(ies).
In order for the computer system to simulate the transmission line and determine or estimate the desired far end response characteristics, the line is mathematically modeled as an RC interconnect or, more commonly, as an RLC interconnect (see Definitions section). For example, many computer aided engineering (CAE) simulation tools conventionally include RLC interconnect simulation for use in simulating the performance of on-chip interconnects. Some conventional methods for determining (see Definitions section) far end response characteristics of RLC interconnects will now be described.
Krylov-subspace-based methods, such as Amoldi algorithm, are commonly used in simulations of interconnect structures with lumped RLC components. For a single wire structure (that is, point-to-point connection) a large number of RLC lumped components are required to simulate the distributed RLC performance of a distributed RLC interconnect. This is relatively inefficient.
Spectre simulations are used in RLC interconnect simulation and can provide accurate results. However, Spectre simulations consume much more simulation time and are inefficient.
Another conventional method is disclosed in the following articles: (i) T. Sakurai, “Approximation of Wiring Delay in MOSFET LSI,” IEEE Journal of Solid-State Circuits, Vol. 18, No. 4, pp. 418-426, August 1983; and (ii) T. Sakurai, “Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI's,” IEEE Transactions on Electron Devices, Vol. 40, No. 1, pp. 118-124, January 1993. (collectively “Sakurai”). In Sakurai, an accurate closed-form solution is disclosed for distributed RC interconnect based on a single pole approximation.
By truncating the transfer function, multi-pole models have been proposed in the last decade to capture the effect of inductance. One example of this method, using two poles is disclosed in A. B. Kahng and S. Muddu, “An Analytical Delay Model for RLC Interconnects,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 12, pp. 1507-1514, December 1997 (“Kahng”). At page 1509, Kahng sets forth the exact transfer function for an RLC interconnect, but then truncates it by expanding the hyperbolic functions present in the transfer function as infinite series, and then collecting terms in this series up to the coefficient of s2. Use this truncated version of the transfer function means that the poles obtained by Kahng are approximate and not exact. Kahng goes on to derive a delay model from the two pole response for the real pole case, the complex pole case and the double pole case.
Another example of this method of truncating the transfer function, using four poles, is disclosed in K. Banerjee and A. Mehrotra, “Accurate Analysis of On-Chip Inductance Effects and Implications for Optimal Repeater Insertion and Technology Scaling,” Proceedings of the IEEE Symposium on VLSI Circuits, pp. 195-198, June 2001 (“Banerjee”). No closed-form solution, however, is provided for the four-pole method. Like Kahng, Banerjee also sets forth the exact transfer function for an RLC interconnect (see Banerjee at equation (1)), including the hyperbolic terms in the denominator. Banerjee then proceeds to truncate this equation by substituting a fourth-order Padé approximation of the transfer function. The fourth-order approximation has terms up to the order of s4, instead of merely up to the order of s2, as in Kahng. Still, the transfer function itself is truncated. Banerjee proceeds to use this truncated version of transfer function to calculate step-response for appropriate residues and approximate poles.
In J. A. Davis and J. D. Meindl, “Compact Distributed RLC Interconnect Models—Part I: Single Line Transient, Time Delay, and Overshoot Expressions,” IEEE Transactions on Electron Devices, Vol. 47, No. 11, pp. 2068-2077, November 2000 (“Davis”), the solution for an open-ended interconnect with a step input signal is rigorously developed. This solution however is highly complicated and not suitable for an exploratory design process.
In Y. Eo, J. Shim, and W. R. Eisenstadt, “A Traveling-Wave-Based Waveform Approximation Technique for the Timing Verification of Single Transmission Lines,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 6, pp. 723-730, June 2002 (“Eo”), a traveling wave analysis (TWA) model has been presented, where the key points of the waveform are determined with a three-pole model and linear or RC approximations are used to connect those key points to construct the waveform. This method is improved in J. Chen and L. He, “Piecewise Linear Model for Transmission Line With Capacitive Loading and Ramp Input,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 6, pp. 928-937, June 2005 (“J. Chen”). In J. Chen, the key points and slopes are more accurately determined with the model described in Davis, and straight lines are used to construct the signal waveforms in different time regions. In both Eo and J. Chen, the output response is divided into a number of time regions where the waveform expressions for each of the regions are different, making the models less compact. Furthermore, none of these aforementioned papers consider frequency dependent effects.
With higher on-chip frequencies, frequency dependent effects in wider interconnect can no longer be ignored. One article dealing with frequency dependent effect was written by the named inventors for this document: G. Chen and E. G. Friedman, “An RLC Interconnect Model Based on Fourier Analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 2, pp. 170-183, February 2005 (“G. Chen Article”). In the G. Chen Article, a Fourier analysis based interconnect model is proposed, where the far end response is approximated by the first several harmonics. Frequency dependent effects can be included in this model; however, the model of the G. Chen Article is only suitable for periodic signals.
Description Of the Related Art Section Disclaimer: To the extent that specific publications are discussed above in this Description of the Related Art Section, these discussions should not be taken as an admission that the discussed publications (for example, published patents) are prior art for patent law purposes. For example, some or all of the discussed publications may not be sufficiently early in time, may not reflect subject matter developed early enough in time and/or may not be sufficiently enabling so as to amount to prior art for patent law purposes. To the extent that specific publications are discussed above in this Description of the Related Art Section, they are all hereby incorporated by reference into this document in their respective entirety(ies).